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DSP/FPGA
VHDL设计举例：伪随机数产生器
发布日期：2009-3-22 11:06:12 文章来源：搜电 浏览次数： [pic]249
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--
-- The following information has been generated by Exemplar Logic and
-- may be freely distributed and modified.
--
-- Design name : pseudorandom
--
-- Purpose : This design is a pseudorandom number generator. This
design
-- will generate an 8-bit random number using the polynomial p(x) =
x + 1.
-- This system has a seed generator and will generate 2**8 - 1
unique
-- vectors in pseudorandom order. These vectors are stored in a ram
which
-- samples the random number every 32 clock cycles. This variance of
a
-- priority encoded seed plus a fixed sampling frequency provides
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