器件名称: I74F50729D
功能描述: Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
文件大小: 94.06KB 共12页
简 介:INTEGRATED CIRCUITS
74F50729 Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
Product specification IC15 Data Handbook 1990 Sep 14
Philips Semiconductors
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered set and reset and metastable immune characteristics
74F50729
FEATURES
Metastable immune characteristics Output skew less than 1.5ns High source current (IOH = 15mA) ideal for clock driver
applications
PIN CONFIGURATION
RD0 1 D0 2 CP0 3 SD0 4 Q0 5 Q0 6 GND 7
14 VCC 13 RD1
See 74F5074 for synchronizing dual D–type flip–flop See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
12 D1 11 10 9 8 CP1 SD1 Q1 Q1
See 74F50728 for synchronizing cascaded dual D–type flip–flop Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F50729 is a dual positive edge–triggered D–type featuring individual data, clock, set and reset inputs; also true and complementary outputs. The 74F50729 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50729 are: τ 135ps and τ 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state re……
