器件名称: EP1C12F100I7ES
功能描述: Cyclone FPGA Family Data Sheet
文件大小: 1353.16KB 共104页
简 介:Section I. Cyclone FPGA Family Data Sheet
This section provides designers with the data sheet specifications for Cyclone devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices. This section contains the following chapters:
■ ■ ■ ■ ■
Chapter 1. Introduction Chapter 2. Cyclone Architecture Chapter 3. Configuration & Testing Chapter 4. DC & Switching Characteristics Chapter 5. Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.
Altera Corporation
Section I–1 Preliminary
Revision History
Cyclone Device Handbook, Volume 1
Section I–2 Preliminary
Altera Corporation
1. Introduction
C51001-1.4
Introduction
The Cyclone field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standa……
