器件名称: MC74AC109DR2
功能描述: Dual JK Positive EdgeTriggered FlipFlop
文件大小: 233.33KB 共9页
简 介:MC74AC109, MC74ACT109 Dual JK Positive EdgeTriggered FlipFlop
The MC74AC109/74ACT109 consists of two high speed completely independent transition clocked JK flipflops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flipflop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
http://onsemi.com
16 1
DIP16 N SUFFIX CASE 648
Outputs Source/Sink 24 mA ′ACT109 Has TTL Compatible Inputs
VCC 16 CD2 15
CD
16 Q2 10
Q Q
J2 14
J
K2 13
K
CP2 12
CP
SD2 11
SD
Q2 9 16
1
SO16 D SUFFIX CASE 751B
1
TSSOP16 DT SUFFIX CASE 948F
CD1 J1
K1
CP1
SD1
Q1
Q1
1 CD1
2 J1
3 K1
4 CP1
5 SD1
6 Q1
7 Q1
8 GND
16
1
EIAJ16 M SUFFIX CASE 966
Figure 1. Pinout; 16Lead Packages Conductors (Top View) PIN ASSIGNMENT
PIN J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 FUNCTION Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
ORDERING INFORMATION
Device MC74AC109N MC74ACT109N MC74AC109D MC74ACT109D MC74AC109DR2 MC74ACT109DR2 MC74AC109DT MC74ACT109DT MC74AC109DTR2 Package PDIP16 PDIP16 SOIC16 SOIC16 SOIC16 SOIC16 TSSOP16 TSSOP16 Shipping 25 Units/Rail 25 Units/Rail 48 Units/Rail 48 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units/Rail 96 Units/Rai……
