器件名称: THC63LVD104S
功能描述: 112MHz 30Bits Color LVDS Receiver
文件大小: 143.26KB 共12页
简 介:THC63LVD104S Rev.1.0
THC63LVD104S
112MHz 30Bits Color LVDS Receiver
General Description
The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 112MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 784Mbps per LVDS channel.Using a 112MHz clock, the data throughput is 490Mbytes per second.
Features
Wide dot clock range: 8-112MHz suited for NTSC,
VGA, SVGA, XGA, and SXGA
PLL requires no external components 50% output clock duty cycle TTL clock edge and position programmable(3 step) Power down mode Low power single 2.5V CMOS design TQFP 64pin Pin compatible with THC63LVD104A Fail-safe for Open CLK Input
Block Diagram
LVDS INPUT SERIAL TO PARALLEL
RA+/RB+/RC+/7 7 7 7 7
CMOS/TTL OUTPUT
RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0 CLKOUT
RD+/RE+/RCLK+/(8 to112MHz)
PLL
CMOS/TTL INPUT
R/F DK PD OE
Copyright 2004 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVD104S Rev.1.0
Pin Out
RARA+ RBRB+ LVCC RCRC+ RCLKRCLK+ LGND RDRD+ RERE+ PGND PVCC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5
49 50 51 52 53……
