器件名称: SL2309
功能描述: Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
文件大小: 248.83KB 共12页
简 介:
SL2309
Description
The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tristated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V.
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 140 MHz operating frequency range Low output clock skew: 50ps-typ Low output clock jitter: 50 ps-typ cycle-to-cycle jitter Low part-to-part output skew: 150 ps-typ 3.3 V power supply range Low power dissipation: 28 mA-max at 66 MHz 44 mA –max at 140 MHz One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThru PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Com……
