器件名称: SL23EP08SC-1T
功能描述: Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
文件大小: 173.77KB 共18页
简 介:Preliminary
SL23EP08
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
x x x 10 to 220 MHz operating frequency range Low output clock skew: 70ps-typ Low output clock Jitter: 50 ps-typ - 50 ps-typ at 166MHz, CL=15pF and VDD=3.3V - 75 ps-typ at 166MHz, CL=15pF and VDD=2.5V Low part-to-part output skew: 150 ps-typ 3.3V to 2.5V power supply range Low power dissipation: x x x x x x x x x x x x x - 22 mA-typ at 66MHz and VDD=3.3V - 20 mA-typ at 66MHz and VDD=2.5V One input drives 8 outputs Multiple configurations and drive options Select mode to bypass PLL or tri-state outputs SpreadThru PLL that allows use of SSCG Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades Printers, MFPs and Digital Copiers PCs and Work Stations Routers, Switchers and Servers Datacom and Telecom High-Speed Digital Embeded Systems
Description
The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to eight (8) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL and a feedback pin (FBK) which can be used to obtain feedback from any one of the output clocks. The SL23EP08 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The s……
