器件名称: AD6472BS
功能描述: 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
文件大小: 114.03KB 共8页
简 介:a
FEATURES Integrated Front End for Single Pair or Two Pair HDSL Systems Meets ETSI Specifications Supports 1168 Kbps and 2.32 Mbps Transmit and Receive Signal Path Functions Receive Hybrid Amplifier, PGA and ADC Transmit DAC, Filter and Differential Outputs Programmable Filters Control and Ancillary Functions Timing Recovery DAC Normal Loopback and Low Power Modes Simple Interface-to-Digital Transceivers Single 5 V Power Supply Power Consumption: 320 mW—(Excluding Driver) Package: 80-Lead MQFP Operating Temperature: –40C to +85 C
2 Pair/1 Pair ETSI Compatible HDSL Analog Front End AD6472
GENERAL DESCRIPTION
The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates. The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is designed to support industry standard digital transceivers. While providing the full analog front end for ETSI standards (two pair or single pair HDSL applications) the AD6472 supports other applications because the architecture allows for bypassing the functional blocks. The normal, low power, and loopback modes and the digital interface combine to make the AD6472 simple to integrate into systems.
FUNCTIONAL BLOCK DIAGRAM
TX_GAIN
12-BIT DAC
2 ANALOG FILTER 2 2
DRIVER
TX 2
TO VCXO
7-BIT DAC
AD6472
CONTROL LOGIC BUFFER 12-BIT ADC 2 2 2 ANALOG FILTER 2 PGA 3 2 HYBRID CIRCUIT RX
REV. 0
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