器件名称: W180_05
功能描述: Peak Reducing EMI Solution
文件大小: 183.01KB 共10页
简 介:W180
Peak Reducing EMI Solution
Features
Cypress PREMIS family offering Generates an EMI optimized clocking signal at the output Selectable output frequency range Single 1.25% or 3.75% down or center spread output Integrated loop filter components Operates with a 3.3V or 5V supply Low power CMOS design Available in 8-pin SOIC (Small Outline Integrated Circuit) FS2 0 0 1 1 FS1 0 1 0 1 -01, 51 (MHz) 8 < FIN < 10 10 < FIN < 15 15 < FIN < 18 18 < FIN < 28 SS% 0 1 Table 1. Modulation Width Selection W180-01, 02, 03 Output W180-51, 52, 53 Output
Fin > Fout > Fin – 1.25% Fin + 0.625% > Fin > – 0.625% Fin > Fout > Fin – 3.75% Fin + 1.875% > Fin > –1.875%
Table 2. Frequency Range Selection W180 Option# -02, 52 (MHz) 8 < FIN < 10 10 < FIN < 15 N/A N/A -03, 53 (MHz) N/A N/A 15 < FIN < 18 18 < FIN < 28
Key Specifications
Supply Voltages:............................................VDD = 3.3V±5% or VDD = 5V±10% Frequency Range:...............................8 MHz < Fin < 28 MHz Cycle to Cycle Jitter: ........................................300 ps (max.) Selectable Spread Percentage:.................... 1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time:...................................5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configurations
SOIC W180-01/51 CLKIN or X1 NC or X2 GND SS% 1 2 3 4 8 7 6 5 FS2 FS1 VDD CLKOUT
X1 XTAL Input
X2
W180
Spread Spectrum Output (EMI suppressed)
W180-02/03 W180-5……
