器件名称: AZ100E111
功能描述: ECL/PECL 1:9 Differential Clock Driver
文件大小: 91.66KB 共6页
简 介:ARIZONA MICROTEK, INC.
AZ10E111 AZ100E111
ECL/PECL 1:9 Differential Clock Driver FEATURES
Low Skew Differential Design Clock Enable VBB Output Operating Range of 4.2V to 5.46V 75kΩ Internal Input Pulldown Resistors Direct Replacement for ON Semi MC10E111 & MC100E111 PACKAGE
PLCC 28 PLCC 28
1 2
PACKAGE AVAILABILITY PART NUMBER
AZ10E111FN AZ100E111FN
MARKING
AZM10E111 AZM100E111
NOTES
1,2 1,2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel. Date code format: “YY” for year followed by “WW” for week.
DESCRIPTION
The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The AZ100E111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single–ended input applications, the VBB reference should be connected to one side of the IN/IN differential input pair. The input signal is then fed to the other IN/IN input. The VBB pin should be used only as a bias for the E111 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within-device, and empirical m……
