器件名称: AZ100LVE210
功能描述: ECL/PECL 1:4, 1:5 Differential Clock Driver
文件大小: 71.9KB 共5页
简 介:ARIZONA MICROTEK, INC.
AZ100LVE210
ECL/PECL 1:4, 1:5 Differential Clock Driver FEATURES
PACKAGE AVAILABILITY Operating Range of 3.0V to 5.5V PACKAGE PART NUMBER MARKING NOTES Low Skew AZM100LVE210 Guaranteed Skew Spec PLCC 28 AZ100LVE210FN 1,2 Differential Design 1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel. VBB Output 2 Date code format: “YY” for year followed by “WW” for week. 75kΩ Internal Input Pulldown Resistors Direct Replacement for ON Semiconductor MC100LVE210 & MC100E210
DESCRIPTION
The AZ100LVE210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE210 offers two selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees. The AZ100LVE210 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single–ended input applications, the VBB reference should be connected to one side of the CLKa/CLKb differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB should only be used as a bias for its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor. Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is met, even if only one side is used. In most applications all eight d……
