器件名称: 1553BRT-EBR
功能描述: Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
文件大小: 217.67KB 共28页
简 介:Advanced v1.1
Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Product Summary
Intended Use
1553 Enhanced Bit Rate Remote Terminal (RT) DMA Backend Interface to External Memory Direct Backend Interface to Devices Space and Avionic Applications
Development System
Complete 1553BRT-EBR Implementation, Implemented in an AX1000
Synthesis and Simulation Support
Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler Simulation: Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators
Key Features
Supports Enhanced Bit Rate 1553 10 Mbps Time-Multiplexed Serial Data Bus Interfaces to External RAM or Directly to Backend Device Synchronous or Asynchronous Backend Interface Encoders and Decoders Operate off 100 MHz Clock Protocol Control and Memory Interface Operates off 50 MHz Clock Interfaces to Standard RS485 Transceivers Programmable Mode Code and Sub-Address Legality for Illegal Command Support Memory Address Mapping Allowing Emulation of Legacy Remote Terminals Fail-Safe State Machines Fully Synchronous Operation
Verification and Compliance
Meets Requirements of Draft SAE AS5682 Standard (2005-10) Actel-Developed Simulation Testbench Implements a Subset of the RT Test Plan (MIL-HDBK-1553A) for Protocol Verification Protocol Control Derived from Core1553BRT, which Is Certified to MIL-STD-1553B (RT Validation Test Plan MIL-HDBK-1553, Appendix A)
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .……
