器件名称: X2P680
功能描述: 0.15mm Structured ASIC
文件大小: 1022.33KB 共14页
简 介:XPressArray-II 0.15mm Structured ASIC
1.0 Key Features
Next-generation 0.15mm hybrid structured ASIC Platform for high-performance 1.5V/1.2V ASICs and FPGAto-ASIC conversions NRE and production cost savings Significant time-to-market advantages Drop-in replacement for cost-reducing Xilinx Virtex-II and Virtex-II Pro and Altera APEX-II and Stratix designs 417K to 3.9M ASIC gates 210MHz system, 500MHz local clock speeds Low power consumption (0.055mW/MHz/gate @ 1.575V) 332Kbits to 4.8Mbits of block RAM memory Up to 5.6Mbits of memory when 50 percent of the logic sites are used for distributed memory 18Kbit initializable dual-port RAM blocks at speeds up to 330MHz Flexible I/O technology, any I/O standard assigned to any I/O pin
Data Sheet
Initializable distributed memory at speeds up to 210MHz Configurable signal, core and I/O power supply pin locations Supports LVTTL, LVCMOS, PCI33, PCI66, PCI-X 133, PCI-X 2.0, GTL/+, HSTL class 1, 2, 3, and 4, SSTL2 class 1 and 2, LVPECL (input), LVDS I/O standards 1.5V, 1.8V, 2.5V, and 3.3V capable I/O True 3.3V tolerance with no external resistor necessary Digital controlled impedance Built-in DDR support LVDS data rates to 1Gbps Up to 1346 user I/Os Comprehensive clock management circuitry Up to eight DLLs and eight PLLs Variety of package options Integrated high-fault coverage scan-test, memory BIST and JTAG
2.0 Product Description
Targeted at medium-density, high-speed, 1.5V and 1.2V ASIC applications and high……
