器件名称: 3DES-EV
功能描述: Core3DES
文件大小: 157.68KB 共13页
简 介:Core3DES
Product Summary
Intended Use
Whenever Data Is Transmitted Across an Accessible Medium (wires, wireless, etc.) E-Commerce Transactions, Where Dedicated Encryption/ Decryption Hardware Can Ease the Load on Servers Personal Security Devices Bank Transactions, Where Financial Security Is Mandatory –
Core Deliverables
Evaluation Version – Compiled RTL Simulation Model Fully Supported in the Actel Libero Integrated Design Environment (IDE) Structural Verilog and VHDL Netlists (with and without I/O pads) Compatible with the Actel Designer Software Place-and-Route Tool Compiled RTL Simulation Model Supported in the Actel Libero IDE Verilog or VHDL Core Source Code Core Synthesis Scripts Fully
Netlist Version
Key Features
Compliant with FIPS PUB 46-3 TECB (TDEA Electronic Codebook) Implementation Per ANSI Standard X9.52 Example Source Code Provided for TCBC, TCFB, and TOFB Modes 168-Bit Cipher Key (consisting of 56-bit cipher keys in 3 stages, with 24 additional parity bits) All Major Actel Device Families Supported Parity Checking Logic for Cipher Key Encryption and Decryption Possible with Same Core 48-Clock Cycle Operation to Encrypt or Decrypt 64 Bits of Data Pause/Resume Functionality to Continue Encryption or Decryption at Will Provides Data Security within a Secure Actel FPGA
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RTL Version – –
Actel-Developed Testbench (Verilog and VHDL)
Synthesis and Simulation Support
Synthesis: Synplicity, Synopsys (Design Compiler/ FPGA Compiler/ FPGA Ex……
