器件名称: 9LPRS535BGLF
功能描述: 48-pin CK505 for Intel Systems
文件大小: 225.43KB 共17页
简 介:Integrated Circuit Systems, Inc.
ICS9LPRS535
Datasheet
48-pin CK505 for Intel Systems
Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential outputs Output Features: Integrated Series Resistors on differential outputs 2 - CPU differential push-pull pairs 4 - SRC differential push-pull pairs 1 - CPU/SRC selectable differential push-pull pair 1 - SRC/DOT selectable differential push-pull pair 1- SRC/Stop_Inputs selectable differential push-pull pair 1 - 25MHz SE1 output for Wake-on-Lan applications 3 - PCI, 33MHz 1 - USB, 48MHz 1 - REF, 14.31818MHz Key Specifications: CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 250ps +/-100ppm frequency accuracy on all clocks Pin Configuration Features/Benefits: Supports spread spectrum modulation, default is 0.5% down spread Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Table 1: CPU Frequency Select Table
FSLC B0b7 0 0 0 0 1 1 1 1
2
FSLB B0b6 0 0 1 1 0 0 1 1
1
FS LA B0b5 0 1 0 1 0 1 0 1
1
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00
SRC MHz
PCI MHz
REF MHz
USB MHz
DOT MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level ……
