器件名称: ADF4001BCP
功能描述: 200 MHz Clock Generator PLL
文件大小: 190.66KB 共16页
简 介:a
FEATURES 200 MHz Bandwidth 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect Hardware-Compatible to the ADF4110/ADF4111/ ADF4112/ADF4113 Typical Operating Current 4.5 mA Ultralow Phase Noise 16-Lead TSSOP 20-Lead Chip Scale Package APPLICATIONS Clock Generation Low Frequency PLLs Low Jitter Clock Source Clock Smoothing Frequency Translation SONET, ATM, ADM, DSLAM, SDM
200 MHz Clock Generator PLL ADF4001
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP CPGND RSET
ADF4001
REFIN 14-BIT R COUNTER 14 R COUNTER LATCH CLK DATA LE SDOUT 24-BIT INPUT REGISTER 22 FUNCTION LATCH LOCK DETECT
REFERENCE
PHASE FREQUENCY DETECTOR
CHARGE PUMP
C……
