器件名称: LMK00334
功能描述: The LMK00334 is a 4-output HCSL fanout buffer
intended for high-frequency, low-jitter clock/data – 30 fs RMS (typical) distribution and level translation. The input clock can
• High PSRR: -72 dBc at 156.25 MHz be selected from two universal inputs or on
文件大小: 1400.85KB 共25页
简 介:LMK00334
www.ti.com SNAS635 – DECEMBER 2013
LMK00334 4-Output PCIe/Gen1/Gen2/Gen3 Clock Buffer/Level Translator
Check for Samples: LMK00334
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FEATURES
3:1 Input Multiplexer – Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock Two Banks with 2 Differential Outputs Each – HCSL, or Hi-Z (Selectable) – Additive RMS Phase Jitter for PCIe Gen3 at 100MHz: – 30 fs RMS (typical) High PSRR: -72 dBc at 156.25 MHz LVCMOS Output with Synchronous Enable Input Pin-Controlled Configuration VCC Core Supply: 3.3 V ± 5% 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5% Industrial Temperature Range: -40°C to +85°C 32-lead WQFN (5 mm x 5 mm)
APPLICATIONS
Clock Distribution and Level Translation for ADCs, DACs, Multi-Gigabit Ethernet, XAUI, Fibre Channel, SATA/SAS, SONET/SDH, CPRI, High-Frequency Backplanes Switches, Routers, Line Cards, Timing Cards Servers, Computing, PCI Express (PCIe 3.0) Remote Radio Units and Baseband Units
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DESCRIPTION
The LMK00334 is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. ……
