器件名称: 74HC00DB
功能描述: Quad 2-input NAND gate
文件大小: 98.98KB 共17页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74HC00; 74HCT00 Quad 2-input NAND gate
Product specication Supersedes data of 1997 Aug 26 2003 Jun 30
Philips Semiconductors
Product specication
Quad 2-input NAND gate
FEATURES Complies with JEDEC standard no. 8-1A ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Specified from 40 to +85 °C and 40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. DESCRIPTION
74HC00; 74HCT00
The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00/74HCT00 provide the 2-input NAND function.
TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC00 the condition is VI = GND to VCC. For 74HCT00 the condition is VI = GND to VCC 1.5 V. FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H OUTPUT nY H H H L PARAMETER propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS 74HC00 CL = 15 pF; VCC = 5 V 7 3.5 22 74HCT00 10 3.5 22 ns pF pF UNIT
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