器件名称: 74HC08
功能描述: Quad 2-input AND gate
文件大小: 109.25KB 共20页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74HC08; 74HCT08 Quad 2-input AND gate
Product specication Supersedes data of 1990 Dec 01 2003 Jul 25
Philips Semiconductors
Product specication
Quad 2-input AND gate
74HC08; 74HCT08
FEATURES Complies with JEDEC standard no. 8-1A ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Specified from 40 to +85 °C and 40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
DESCRIPTION The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT08 provide the 2-input AND function.
TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC08: the condition is VI = GND to VCC. For 74HCT08: the condition is VI = GND to VCC 1.5 V. FUNCTION TABLE INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H OUTPUT nY L L L H PARAMETER propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS 74HC08 CL = 15 pF; VCC = 5 V 7 3.5 10 74HCT08 11 3.5 20 ns pF pF UNIT
2003 Jul 25
2
Philips……
