器件名称: 74VHCT132AMTR
功能描述: QUAD 2-INPUT SCHMITT NAND GATE
文件大小: 53.51KB 共7页
简 介:
74VHCT132A
QUAD 2-INPUT SCHMITT NAND GATE
PRELIMINARY DATA
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HIGH SPEED: tPD = 6.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 A (MAX.) at TA = 25 oC TYPICAL HYSTERESIS: 0.7V at VCC = 4.5V POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 132 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (Max.)
SOP
PACKAGE SOP TSSOP T UBE 74VHCT132AM
TSSOP
T& R 74VHCT132AMTR 74VHCT132ATTR
ORDER CODES
DESCRIPTION The 74VHCT132A is an advanced high-speed CMOS QUAD 2-INPUT SCHMITT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. Pin configuration and function are the same as those of the VHCT00A but the VHCT132A has hysteresis. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
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74VHCT132A
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 ……
