器件名称: 74HC243N
功能描述: Quad bus transceiver; 3-state
文件大小: 92.36KB 共17页
简 介:74HC243
Quad bus transceiver; 3-state
Rev. 03 — 12 November 2004 Product data sheet
1. General description
The 74HC243 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC243 is specied in compliance with JEDEC standard no. 7A. The 74HC243 is a quad bus transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 74HC243 is designed for 4-line asynchronous 2-way data communications between data buses. The output enable inputs (OEA and OEB) can be used to isolate the buses. The 74HC243 is similar to the 74HC242 but has non-inverting (true) outputs.
2. Features
s s s s s Non-inverting 3-state outputs 2-way asynchronous data bus communication Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specied from 40 °C to +80 °C and from 40 °C to +125 °C.
Philips Semiconductors
74HC243
Quad bus transceiver; 3-state
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns. Symbol tPHL, tPLH CI CI/O CPD
[1]
Parameter propagation delay An to Bn; Bn to An input capacitance input/output capacitance power dissipation capacitance per transceiver
Conditions CL = 15 pF; VCC = 5 V
Min -
Typ 6 3.5 10 26
Max -
Unit ns pF pF pF
VI = GND to VCC
[1]
-
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD × ……
