器件名称: M74HC4075B1R
功能描述: TRIPLE 3 INPUT OR GATE
文件大小: 232.73KB 共9页
简 介:M54HC4075 M74HC4075
TRIPLE 3 INPUT OR GATE
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HIGH SPEED tPD = 8 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 4075B
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HC4075F1R M74HC4075M1R M74HC4075B1R M74HC4075C1R
DESCRIPTION The M54/74HC4075 is a high speed CMOS TRIPLE 3-INPUT OR GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 4 stages including buffered output, which gives high noise immunity and a stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
NC = No Internal Connection
October 1992
1/9
M54/M74HC4075
TRUTH TABLE
A L H X X B L X H X C L X X H Y L H H H
IEC LOGIC SYMBOL
PIN DESCRIPTION
PIN No 3, 1, 11 4, 2, 12 5, 8, 13 6, 9, 10 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage
SCHEMATIC CIRCUIT (Per Gate)
ABSOLUTE MAXIMUM RATINGS……
