器件名称: MC54-74HC366
功能描述: Hex 3-State Inverting Buffer with Common Enables
文件大小: 163.54KB 共5页
简 介:MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex 3-State Inverting Buffer with Common Enables
High–Performance Silicon–Gate CMOS
The MC54/74HC366 is identical in pinout to the LS366. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is a high–speed hex buffer with 3–state outputs and two common active–low Output Enables. When either of the enables is high, the buffer outputs are placed into high–impedance states. The HC366 has inverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 78 FETs or 19.5 Equivalent Gates
MC54/74HC366
J SUFFIX CERAMIC PACKAGE CASE 620–10
1
16
16 1
N SUFFIX PLASTIC PACKAGE CASE 648–08
ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN Ceramic Plastic
PIN ASSIGNMENT LOGIC DIAGRAM
OUTPUT ENABLE 1 A0 3 Y0 5 Y1 7 Y2 9 Y3 11 Y4 13 Y5 Y0 A1 Y1 A2 A2 6 Y2 GND A3 10 A4 12 A5 OUTPUT ENABLE 1 1 14 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OUTPUT ENABLE 2 A5 Y5 A4 Y4 A3 Y3
A0 A1
2 4
FUNCTION TABLE
Inputs Enable 1 L L H X Enable 2 L L X H A L H X X Output Y H L Z Z
OUTPUT ENABLE 2 15
PIN 16 = VCC PIN 8 = GND
X = don’t care Z = high impedance
10/95
Motorola, Inc. 1995
1
REV 6
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