器件名称: I74F786N
功能描述: 4-bit asynchronous bus arbiter
文件大小: 95.19KB 共12页
简 介:INTEGRATED CIRCUITS
74F786 4-bit asynchronous bus arbiter
Product specification IC15 Data Handbook 1991 Feb 14
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit asynchronous bus arbiter
74F786
FEATURES
Arbitrates between 4 asynchronous inputs Separate grant output for each input Common output enable On board 4 input AND gate Metastable–free outputs Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F786 is an asynchronous 4–bit arbiter designed for high speed real–time applications. The priority of arbitration is determined on a first–come first–served basis. Separate bus grant (BGn) outputs are available to indicate which one of the request inputs is served by the arbitration logic. All BGn outputs are enabled by a common enable (EN) pin. In order to generate a bus request signal a separate 4 input AND gate is provided which may also be used as an independent AND gate. Unused bus request (BR) inputs may be disabled by tying them high.
The 74F786 is designed so that contention between two or more request signals will not glitch or display a metastable condition. In this situation an increase in the BRn to BGn tPHL may be observed. A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5sec. Where: h = Typical propagation delay through the device and t and To are device parameters derived from test results and can most nearly be defined as: t = A function of the rate at which a latch in a metastable state resolves ……
