器件名称: UD61466
功能描述: 64K x 4 DRAM
文件大小: 174.93KB 共14页
简 介:Maintenance only
Features
UD61466
64K x 4 DRAM
SCM facilitates faster data operation with predefined row address. Via 8 address inputs the 16 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address. After the row address hold time the column address can be applied. During the Read cycle the address transfer is not latched by the falling edge at the CAS input, so that the column address must be applied until the data are valid at the output. During Write the column address is taken over with the falling edge of the control signal CAS, or W, that becomes active as the last. The selection of one or more memory circuits can be made via the RAS input. Data Output Control The usual state of the data output is the High-Z state. Whenever CAS is inactive (HIGH), Q will float (High-Z). Thus, CAS functions as data output control. After access time, in case of a Read cycle, the output is activated, and it contains the logic 0“ or 1“. The memory cycle being a Read, Read-Write or a Write cycle (W-controlled), Q changes from High-Z state to the active state (0“ or 1“). After access time, the contents of the selected cell will be available, with the exception of the Write cycle. The output remains active until CAS becomes inactive, irrespective of RAS becoming inactive or not. The memory cycle being a Write cycle (CAS-controlled), the data output keeps its High-Z state throughout the whole cycle. This conf……
