器件名称: VDS6608A4A
功能描述: Synchronous DRAM(2M X 8 Bit X 4 Banks)
文件大小: 521.98KB 共8页
简 介:V-Data
Synchronous DRAM General Description
The VDS6608A4A are four-bank Synchronous DRAMs organized as 2,097,152 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications
VDS6608A4A
2M x 8 Bit x 4 Banks Features
JEDEC standard LVTTL 3.3V power supply MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8,& full page) -Burst Type (sequential & Interleave) 4 banks operation All inputs are sampled at the positive edge of the system clock Burst Read single write operation Auto & Self refresh 4096 refresh cycle DQM for masking Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No. VDS6608A4A-75 Frequency 133Mhz Interface LVTTL Package 400mil 54pin TSOPII
Pin Assignment
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3
54
Vss DQ7 VssQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC/RFU DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
53
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54-pin plastic TSOP II 400 mil
Rev 1 April, 2001
1
V-Data
Pin Description
PIN CK CKE NAME System Clock Clock Enable FU……
