器件名称: 74F109
功能描述: Positive J-K positive edge-triggered flip-flops
文件大小: 85.03KB 共10页
简 介:INTEGRATED CIRCUITS
74F109 Positive J-K positive edge-triggered flip-flops
Product specification IC15 Data Handbook 1990 Oct 23
Philips Semiconductors
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation. TYPE 74F109 TYPICAL fmax 125MHz TYPICAL SUPPLY CURRENT (TOTAL) 12.3mA
PIN CONFIGURATION
RD0 J0 K0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD1 J1 K1 CP1 SD1 Q1 Q1
SF00135
ORDERING INFORMATION
ORDER CODE DESC……
