器件名称: 74HC297
功能描述: Digital phase-locked-loop filter
文件大小: 101.43KB 共12页
简 介:INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT297 Digital phase-locked-loop filter
Product specication File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specication
Digital phase-locked-loop lter
FEATURES Digital design avoids analog compensation errors Easily cascadable for higher order loops Useful frequency range: – DC to 55 MHz typical (K-clock) – DC to 35 MHz typical (I/D-clock) Dynamically variable bandwidth Very narrow bandwidth attainable Power-on reset Output capability: standard/bus driver ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT297 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT297 are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-n counter, to build first order phase-locked-loops. Both EXCLUSIVE-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop funct……
