器件名称: 74HC377DB
功能描述: Octal D-type flip-flop with data enable; positive-edge trigger
文件大小: 60.66KB 共7页
简 介:INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT377 Octal D-type flip-flop with data enable; positive-edge trigger
Product specication File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specication
Octal D-type ip-op with data enable; positive-edge trigger
FEATURES Ideal for addressable register applications Data enable for address and data synchronization applications Eight positive-edge triggered D-type flip-flops See “273” for master reset version See “373” for transparent latch version See “374” for 3-state version Output capability: standard ICC category: MSI GENERAL DESCRIPTION
74HC/HCT377
The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.
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