器件名称: 74HC74
功能描述: Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
文件大小: 133.38KB 共8页
简 介:74HC74 Dual D FlipFlop with Set and Reset
HighPerformance SiliconGate CMOS
The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flipflops with individual Set, Reset, and Clock inputs. Information at a Dinput is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flipflop. The Set and Reset inputs are asynchronous.
Features
14 1
http://onsemi.com MARKING DIAGRAMS
14 SOIC14 D SUFFIX CASE 751A 1 HC74G AWLYWW
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 128 FETs or 32 Equivalent Gates PbFree Packages are Available
14 14 1 TSSOP14 DT SUFFIX CASE 948G 1 HC 74 ALYW G G
HC74 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = PbFree Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
Semiconductor Components Industries, LLC, 2007
February, 2007 Rev. 0
1
Publication Order Number: 74HC……
