器件名称: 74HCT4040D
功能描述: 12-stage binary ripple counter
文件大小: 137.51KB 共24页
简 介:74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 03 — 14 September 2005 Product data sheet
1. General description
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specied in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle ip-op.
2. Features
s Multiple package options s Complies with JEDEC standard no. 7A s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specied from 40 °C to +85 °C and from 40 °C to +125 °C
3. Applications
s Frequency dividing circuits s Time delay circuits s Control counters
4. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol tPHL, tPLH Parameter propagation delay CP to Q0 Qn to Qn+1 CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V 14 8 ns ns Conditions Min Typ Max Unit Type 74HC4040
Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 1: Quick reference data …continued GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol fmax Ci CPD Parameter maximum operating frequency input capacitance power dissipation capacitanc……
