器件名称: ADD8608A8A-75B
功能描述: Double Data Rate SDRAM
文件大小: 549.6KB 共9页
简 介:A-Data
Revision History Revision 1 ( Dec. 2001 )
1.Fister release.
ADD8608A8A
Revision 2 ( Apr. 2002 )
1. 2. 3. 4. Changed module current specification. Add Performance range. Changed AC Characteristics. Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002
1
A-Data
Double Data Rate SDRAM General Description
The ADD8608A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 8,392,608 words x 8 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and /CK. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications
ADD8608A8A
8M x 8 Bit x 4 Banks Features
2.5V for VDDQ power supply SSTL_2 interface MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave) 4 banks operation Differential clock input (CK, /CK) operation Double data rate interface Auto & Self refresh 8192 refresh cycle DQM for masking Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No. ADD8608A8A-75BA ADD8608A8A-75B Frequency 133Mhz(7.5ns/CL=2) 133Mhz(7.5ns/CL=2.5) Interface SSTL_2 Package 400mil 66pin TSOPII
Pin Assignment
VD D D Q0 VDD Q NC DQ1 VSSQ NC DQ2 VDD Q NC DQ3 VSSQ NC NC V DDQ NC NC
VD D NC 1
NC
WE CAS RAS CS NC BS……