使用了XPS中建立和导入IP向导(简称ipwiz),默认的源码文件只有hdl/verilog目录下的"userlogic.v"和hdl/vhdl目录下的"ipname.vhd"文件。当我们的设计变复杂了,需要更多的设计文件如.v、.vhd、.ngc等文件和多个模块/实体的时候,如果不进行一些设置,编译器会提示找不到module的错误提示:ERROR:HDLCompiler:Instantiating <xx> from unknown module <xx>。怎样才能让编译器找到我们所有的设计文件和模块呢?
例如,这几天我做了一个字符VGA的IP核,IP的名字是axi_vga,hdl目录下的设计文件结构如下:
中,我们通过修改这个文件将告诉ARM PS系统,这个IP有8个输出引脚,并通过修改system.ucf约束连接到zynq的外部引脚上。.mpd文件内容如下: 1 ###################################################################2 ##
3 ## Name : axi_vga
4 ## Desc : Microprocessor Peripheral Description
5 ## : Automatically generated by PsfUtility
6 ##
7 ###################################################################
8
9 BEGIN axi_vga
10
11 ## Peripheral Options
12 OPTION IPTYPE = PERIPHERAL
13 OPTION IMP_NETLIST = TRUE
14 OPTION HDL = MIXED
15 OPTION IP_GROUP = MICROBLAZE:USER
16 OPTION DESC = AXI_VGA
17 OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
18
19
20 ## Bus Interfaces
21 BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
22
23 ## Generics for VHDL or Parameters for Verilog
24 PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
25 PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
26 PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
27 PARAMETER C_USE_WSTRB = 0, DT = INTEGER
28 PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
29 PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
30 PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
31 PARAMETER C_FAMILY = virtex6, DT = STRING
32 PARAMETER C_NUM_REG = 1, DT = INTEGER
33 PARAMETER C_NUM_MEM = 1, DT = INTEGER
34 PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
35 PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
36 PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
37
38 ## Ports
39 PORT HS = "", DIR = O
40 PORT VS = "", DIR = O
41 PORT RED = "", DIR = O, VEC=[3:0]
42 PORT GREEN = "", DIR = O, VEC=[3:0]
43 PORT BLUE = "", DIR = O, VEC = [3:0]
44 PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
45 PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
46 PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
47 PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
48 PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
49 PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
50 PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
51 PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
52 PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
53 PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
54 PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
55 PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
56 PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
57 PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
58 PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
59 PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
60 PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
61 PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
62 PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
63
64 END
其中39~43行
PORT HS = "", DIR = O PORT VS = "", DIR = O PORT RED = "", DIR = O, VEC=[3:0] PORT GREEN = "", DIR = O, VEC=[3:0] PORT BLUE = "", DIR = O, VEC = [3:0]
是定义的对外引脚信号,其他均为AXI内部互联接口。
.prj文件
.prj该包含了IP所需要使用的文件以及路径。Ipwiz生成默认的.prj文件内容如下:
1 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"2 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
3 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
4 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
5 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
6 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
7 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
8 vhdl axi_lite_ipif_v1_01_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd"
9 vhdl axi_lite_ipif_v1_01_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd"
10 vhdl axi_lite_ipif_v1_01_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd"
11 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd"
12 verilog axi_vga_v1_00_a "../hdl/verilog/user_logic.v"
13 vhdl axi_vga_v1_00_a "../hdl/vhdl/axi_vga.vhd"
可以看到,这个IP除了使用ISE的提供的库文件(来完成AXI接口和协议),并把它们定义成库proc_common_v3_00_a和库axi_lite_ipif_v1_01_a;同时这个IP还使用到了两个默认生成的设计源文件user_logic.v和axi_vga.vhd,并把它们定义到库axi_vga_v1_00_a中,而这个库就是我们IP的名字。
.pao(Peripheral Analyze Order,编译顺序)文件
.pao文件定义了需要编译哪写HDL文件且以什么样的顺序编译。ipwiz生成的.pao文件内容如下:
################################################################################ Filename: D:/_prj/Xilinx/Zynq_new/AXI_Master_VGA_2/pcores/axi_vga_v1_00_a/data/axi_vga_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Mon Nov 12 15:38:45 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib axi_lite_ipif_v1_01_a all
lib axi_vga_v1_00_a user_logic verilog
lib axi_vga_v1_00_a axi_vga vhdl
可以看到,对于在.prj文件中定义的文件和库,编译器会编译库proc_common_v3_00_a和库axi_lite_ipif_v1_01_a里面的所有实体;同时也将使用axi_vga_v1_00_a库中的user_logic实体,它来自于一个verilog类型文件,将使用axi_vga实体,它来自于一个vhdl类型的文件。同时编译顺序也确定下来。
由以上的分析可以知道,data目录下的文件信息都非常重要,.mpd文件定义了外设的接口,.prj文件定义了IP所需要使用的文件以及路径,而.pao定义了需要编译哪写源文件以及使用什么样的顺序进行编译。知道了这些,对于最开始出现的那个问题,我们就知道该如何解决了:
1、 修改data目录下的.prj文件,把所有设计源文件都添加到其中;
2、 修改data目录下的.pao文件,把所有设计实体都添加到其中。
修改完的.prj文件内容如下
1 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"2 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
3 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
4 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
5 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
6 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
7 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
8 vhdl axi_lite_ipif_v1_01_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd"
9 vhdl axi_lite_ipif_v1_01_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd"
10 vhdl axi_lite_ipif_v1_01_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd"
11 vhdl proc_common_v3_00_a"C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd"
12 verilog axi_vga_v1_00_a "../hdl/verilog/DPBRAM.v"
13 verilog axi_vga_v1_00_a "../hdl/verilog/CGROM.v"
14 verilog axi_vga_v1_00_a "../hdl/verilog/vga_sync.v"
15 vhdl axi_vga_v1_00_a "../hdl/vhdl/DCM1.vhd"
16 verilog axi_vga_v1_00_a "../hdl/verilog/user_logic.v"
17 vhdl axi_vga_v1_00_a "../hdl/vhdl/axi_vga.vhd"
修改完的.pao文件内容如下
1 ##############################################################################2 ## Filename: D:/_prj/Xilinx/Zynq_new/AXI_Master_VGA_2/pcores/axi_vga_v1_00_a/data/axi_vga_v2_1_0.pao
3 ## Description: Peripheral Analysis Order
4 ## Date: Mon Nov 12 15:38:45 2012 (by Create and Import Peripheral Wizard)
5 ##############################################################################
6
7 lib proc_common_v3_00_a all
8 lib axi_lite_ipif_v1_01_a all
9 lib axi_vga_v1_00_a user_logic verilog
10 lib axi_vga_v1_00_a vga_sync verilog
11 lib axi_vga_v1_00_a DCM1 vhdl
12 lib axi_vga_v1_00_a DPBRAM verilog
13 lib axi_vga_v1_00_a CGROM verilog
14 lib axi_vga_v1_00_a axi_vga vhdl
修改完成后,“rescan user repositories“将所做的修改更新到工程中,然后再进行DRC检查和生成bit文件,错误ERROR:HDLCompiler:Instantiating <xx> from unknown module <xx>消失,XST综合成功。
==========================================
注意:
1、修改.prj文件时,注意文件的类型是verilog还是vhdl
2、修改.pao文件时,最好按照元件的例化顺序添加。