器件名称: 74VHC132
功能描述: QUAD 2-INPUT SCHMITT NAND GATE
文件大小: 235.67KB 共11页
简 介:74VHC132
QUAD 2-INPUT SCHMITT NAND GATE
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HIGH SPEED: tPD = 3.9 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 A (MAX.) at TA=25°C TYPICAL HYSTERESIS: Vh = 1V at VCC = 4.5V POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 132 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)
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Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHC132MTR 74VHC132TTR
DESCRIPTION The 74VHC132 is an advanced high-speed CMOS QUAD 2-INPUT SCHMITT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.
Pin configuration and function are the same as those of the 74VHC00 but the 74VHC132 has hysteresis. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 4
1/11
74VHC132
Figure 2: Input Equivalent Circuit Table 2: Pin Description
PIN N° 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B……
