器件名称: 74LVQ240SJ
功能描述: Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
文件大小: 65.75KB 共6页
简 介:74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
June 1993 Revised June 2001
74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density.
Features
s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 s 4 kV minimum ESD immunity
Ordering Code:
Order Number 74LVQ240SC 74LVQ240SJ 74LVQ240QSC Package Number M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names OE1, OE2 I0–I7 O0–O7 Description 3-STATE Output Enable Inputs Inputs Outputs
Truth Tables
Inputs OE1 In L H X Inputs OE2 L L H
H = HIGH Voltage Level X = Immaterial
Outputs (Pins 12, 14, 16, 18) H L Z Outputs In L H X
L = LOW Voltage Level Z = High Impedance
Connection Diagram
L L H
(……
