器件名称: 74LVQ240SJ
功能描述: Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
文件大小: 88.61KB 共6页
简 介:74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
May 1998
74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density.
Features
n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75 n 4 kV minimum ESD immunity
Ordering Code:
Order Number 74LVQ240SC 74LVQ240SJ 74LVQ240QSC Package Number M20B M20D MQA20 Package Description 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Assignment, SOIC and QSOP
DS011611-1
Pin Descriptions
Pin Names OE1, OE2 I0–I7 O0–O7 Inputs Outputs Description 3-STATE Output Enable Inputs
DS011611-2
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H
H = HIGH Voltage Level X = Immaterial
Outputs In L H X (Pins 12, 14, 16, 18) H L Z Outputs In L H X
L = LOW Voltage Level Z = H……
